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The Optimal Decision Combination in Semiconductor Manufacturing

Author

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  • Sungwook Yoon

    (Business School, Kwangwoon University, 26 Kwangwoon-gil (447-1, Wolgye-dong), Nowon-Gu, Seoul 139-701, Korea)

  • Jihyun Kim

    (Business School, Kwangwoon University, 26 Kwangwoon-gil (447-1, Wolgye-dong), Nowon-Gu, Seoul 139-701, Korea)

  • Sukjae Jeong

    (Business School, Kwangwoon University, 26 Kwangwoon-gil (447-1, Wolgye-dong), Nowon-Gu, Seoul 139-701, Korea)

Abstract

Wafer fabrication is a capital-intensive and highly complex manufacturing process. In a wafer fabrication facility (fab), wafers are grouped as a lot to go through repeated sequences of operations to build circuitry. Lot scheduling is an important task for manufacturers in order to improve production efficiency and satisfy customers’ demands of on-time delivery. Cycle time and average work-in-process reduction while meeting customers’ requirements play an important role in improving the competitiveness and sustainability of a semiconductor manufacturer. In this research, we propose the optimal combination rules for lot scheduling problems in wafer fabs, focusing on three complex areas of decision making: lot release control, batch sizing, and dispatching lots to enhance competitiveness and sustainability of a semiconductor facility.

Suggested Citation

  • Sungwook Yoon & Jihyun Kim & Sukjae Jeong, 2017. "The Optimal Decision Combination in Semiconductor Manufacturing," Sustainability, MDPI, vol. 9(10), pages 1-19, October.
    • Handle: RePEc:gam:jsusta:v:9:y:2017:i:10:p:1788-:d:113949
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    References listed on IDEAS

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    1. Jaeseok Huh & Inbeom Park & Seongmin Lim & Bohyung Paeng & Jonghun Park & Kwanho Kim, 2018. "Learning to Dispatch Operations with Intentional Delay for Re-Entrant Multiple-Chip Product Assembly Lines," Sustainability, MDPI, vol. 10(11), pages 1-21, November.

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