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Learning to Dispatch Operations with Intentional Delay for Re-Entrant Multiple-Chip Product Assembly Lines

Author

Listed:
  • Jaeseok Huh

    (Department of Industrial Engineering and Institute for Industrial Systems Innovation, Seoul National University, 1 Gwanak-ro, Gwanak-gu, Seoul 151-744, Korea)

  • Inbeom Park

    (Department of Industrial Engineering and Institute for Industrial Systems Innovation, Seoul National University, 1 Gwanak-ro, Gwanak-gu, Seoul 151-744, Korea)

  • Seongmin Lim

    (Department of Industrial Engineering and Institute for Industrial Systems Innovation, Seoul National University, 1 Gwanak-ro, Gwanak-gu, Seoul 151-744, Korea)

  • Bohyung Paeng

    (Department of Industrial Engineering and Institute for Industrial Systems Innovation, Seoul National University, 1 Gwanak-ro, Gwanak-gu, Seoul 151-744, Korea)

  • Jonghun Park

    (Department of Industrial Engineering and Institute for Industrial Systems Innovation, Seoul National University, 1 Gwanak-ro, Gwanak-gu, Seoul 151-744, Korea)

  • Kwanho Kim

    (Department of Industrial and Management Engineering, Incheon National University, 119 Academy-ro, Yeonsu-gu, Incheon 407-772, Korea)

Abstract

As the demand for small devices with embedded flash memory increases, semiconductor manufacturers have been recently focusing on producing high-capacity multiple-chip products (MCPs). Due to the frequently re-entrant lots between the die attach (DA) and wire bonding (WB) assembly stages in MCP production, increased flow time and decreased resource utilization are unavoidable. In this paper, we propose a dispatcher based on artificial neural networks, which minimizes the flow time while maintaining high utilization of resources at the same time through exploiting the possible intentional delays on DA stage. Specifically, the proposed dispatcher learns the assignment preferences between available lots and DA resources based on assembly line data generated by using a simulator, then the proposed dispatcher performs lot dispatching decisions by considering the intentional delays. The numerical experiments were performed under various configurations of the MCP assembly lines, and the results show that the proposed dispatcher outperformed the existing methods.

Suggested Citation

  • Jaeseok Huh & Inbeom Park & Seongmin Lim & Bohyung Paeng & Jonghun Park & Kwanho Kim, 2018. "Learning to Dispatch Operations with Intentional Delay for Re-Entrant Multiple-Chip Product Assembly Lines," Sustainability, MDPI, vol. 10(11), pages 1-21, November.
    • Handle: RePEc:gam:jsusta:v:10:y:2018:i:11:p:4123-:d:181797
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    References listed on IDEAS

    as
    1. Sungwook Yoon & Jihyun Kim & Sukjae Jeong, 2017. "The Optimal Decision Combination in Semiconductor Manufacturing," Sustainability, MDPI, vol. 9(10), pages 1-19, October.
    2. Kanet, John J., 1986. "Tactically delayed versus non-delay scheduling: An experimental investigation," European Journal of Operational Research, Elsevier, vol. 24(1), pages 99-105, January.
    3. John J. Kanet & V. Sridharan, 2000. "Scheduling with Inserted Idle Time: Problem Taxonomy and Literature Review," Operations Research, INFORMS, vol. 48(1), pages 99-110, February.
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