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A Machine Learning Approach for Improving Wafer Acceptance Testing Based on an Analysis of Station and Equipment Combinations

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  • Chien-Chih Wang

    (Department of Industrial Engineering and Management, Ming Chi University of Technology, New Taipei City 24303, Taiwan)

  • Yi-Ying Yang

    (Department of Industrial Engineering and Management, Ming Chi University of Technology, New Taipei City 24303, Taiwan)

Abstract

Semiconductor manufacturing is a complex and lengthy process. Even with their expertise and experience, engineers often cannot quickly identify anomalies in an extensive database. Most research into equipment combinations has focused on the manufacturing process’s efficiency, quality, and cost issues. There has been little consideration of the relationship between semiconductor station and equipment combinations and throughput. In this study, a machine learning approach that allows for the integration of control charts, clustering, and association rules were developed. This approach was used to identify equipment combinations that may harm production processes by analyzing the effect on Vt parameters of the equipment combinations used in wafer acceptance testing (WAT). The results showed that when the support is between 70% and 80% and the confidence level is 85%, it is possible to quickly select the specific combinations of 13 production stations that significantly impact the Vt values of all 39 production stations. Stations 046000 (EH308), 049200 (DW005), 049050 (DI303), and 060000 (DC393) were found to have the most abnormal equipment combinations. The results of this research will aid the detection of equipment errors during semiconductor manufacturing and assist the optimization of production scheduling.

Suggested Citation

  • Chien-Chih Wang & Yi-Ying Yang, 2023. "A Machine Learning Approach for Improving Wafer Acceptance Testing Based on an Analysis of Station and Equipment Combinations," Mathematics, MDPI, vol. 11(7), pages 1-14, March.
    • Handle: RePEc:gam:jmathe:v:11:y:2023:i:7:p:1569-:d:1105378
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    References listed on IDEAS

    as
    1. Hyun Joong Yoon & Junjae Chae, 2019. "Simulation Study for Semiconductor Manufacturing System: Dispatching Policies for a Wafer Test Facility," Sustainability, MDPI, vol. 11(4), pages 1-21, February.
    2. Yong Jin Suh & Jin Young Choi, 2022. "Efficient Fab facility layout with spine structure using genetic algorithm under various material-handling considerations," International Journal of Production Research, Taylor & Francis Journals, vol. 60(9), pages 2816-2829, May.
    3. Eduardo e Oliveira & Vera L. Miguéis & José L. Borges, 2022. "On the influence of overlap in automatic root cause analysis in manufacturing," International Journal of Production Research, Taylor & Francis Journals, vol. 60(21), pages 6491-6507, November.
    4. Chia-Yu Hsu & Wei-Chen Liu, 2021. "Multiple time-series convolutional neural network for fault detection and diagnosis and empirical study in semiconductor manufacturing," Journal of Intelligent Manufacturing, Springer, vol. 32(3), pages 823-836, March.
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