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Ferroelectric compute-in-memory annealer for combinatorial optimization problems

Author

Listed:
  • Xunzhao Yin

    (Zhejiang University
    Key Laboratory of CS&AUS of Zhejiang Province)

  • Yu Qian

    (Zhejiang University)

  • Alptekin Vardar

    (Fraunhofer IPMS)

  • Marcel Günther

    (Fraunhofer IPMS)

  • Franz Müller

    (Fraunhofer IPMS)

  • Nellie Laleni

    (Fraunhofer IPMS)

  • Zijian Zhao

    (University of Notre Dame)

  • Zhouhang Jiang

    (University of Notre Dame)

  • Zhiguo Shi

    (Zhejiang University
    Key Laboratory of CS&AUS of Zhejiang Province)

  • Yiyu Shi

    (University of Notre Dame)

  • Xiao Gong

    (National University of Singapore)

  • Cheng Zhuo

    (Zhejiang University
    Key Laboratory of CS&AUS of Zhejiang Province)

  • Thomas Kämpfe

    (Fraunhofer IPMS)

  • Kai Ni

    (University of Notre Dame)

Abstract

Computationally hard combinatorial optimization problems (COPs) are ubiquitous in many applications. Various digital annealers, dynamical Ising machines, and quantum/photonic systems have been developed for solving COPs, but they still suffer from the memory access issue, scalability, restricted applicability to certain types of COPs, and VLSI-incompatibility, respectively. Here we report a ferroelectric field effect transistor (FeFET) based compute-in-memory (CiM) annealer for solving larger-scale COPs efficiently. Our CiM annealer converts COPs into quadratic unconstrained binary optimization (QUBO) formulations, and uniquely accelerates in-situ the core vector-matrix-vector (VMV) multiplication operations of QUBO formulations in a single step. Specifically, the three-terminal FeFET structure allows for lossless compression of the stored QUBO matrix, achieving a remarkably 75% chip size saving when solving Max-Cut problems. A multi-epoch simulated annealing (MESA) algorithm is proposed for efficient annealing, achieving up to 27% better solution and ~ 2X speedup than conventional simulated annealing. Experimental validation is performed using the first integrated FeFET chip on 28nm HKMG CMOS technology, indicating great promise of FeFET CiM array in solving general COPs.

Suggested Citation

  • Xunzhao Yin & Yu Qian & Alptekin Vardar & Marcel Günther & Franz Müller & Nellie Laleni & Zijian Zhao & Zhouhang Jiang & Zhiguo Shi & Yiyu Shi & Xiao Gong & Cheng Zhuo & Thomas Kämpfe & Kai Ni, 2024. "Ferroelectric compute-in-memory annealer for combinatorial optimization problems," Nature Communications, Nature, vol. 15(1), pages 1-11, December.
    • Handle: RePEc:nat:natcom:v:15:y:2024:i:1:d:10.1038_s41467-024-46640-x
    DOI: 10.1038/s41467-024-46640-x
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    References listed on IDEAS

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