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SEU emulation in industrial SoCs combining microprocessor and FPGA

Author

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  • Villalta, Igor
  • Bidarte, Unai
  • Gómez-Cornejo, Julen
  • Jiménez, Jaime
  • Lázaro, Jesús

Abstract

FPGAs (Field-Programmable Gate Array) and FPGA-based SoCs (System-on-chip) are electronic devices which offer high computational performance and low time-to-market for low and medium production volumes. They are gaining popularity in critical sectors, such as automotive, aerospace, avionics and railway, making their reliability evaluation mandatory. FPGAs are notoriously sensitive to SEUs (Single Event Upsets), which are random memory errors provoked by radiation particles. The failure rate of an FPGA varies with the implemented design, depending on the amount of used resources and the implemented redundancy schemes among others. FPGA-based circuits are being used in complex safety-critical engineering systems that are designed in compliance with dependability regulations. This work presents an emulation-based methodology for estimating the failure rate of designs implemented in FPGA SoCs, which is a key data in this scenario.

Suggested Citation

  • Villalta, Igor & Bidarte, Unai & Gómez-Cornejo, Julen & Jiménez, Jaime & Lázaro, Jesús, 2018. "SEU emulation in industrial SoCs combining microprocessor and FPGA," Reliability Engineering and System Safety, Elsevier, vol. 170(C), pages 53-63.
    • Handle: RePEc:eee:reensy:v:170:y:2018:i:c:p:53-63
    DOI: 10.1016/j.ress.2017.09.028
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    References listed on IDEAS

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    1. McNelles, Phillip & Zeng, Zhao Chang & Renganathan, Guna & Lamarre, Greg & Akl, Yolande & Lu, Lixuan, 2016. "A comparison of Fault Trees and the Dynamic Flowgraph Methodology for the analysis of FPGA-based safety systems Part 1: Reactor trip logic loop reliability analysis," Reliability Engineering and System Safety, Elsevier, vol. 153(C), pages 135-150.
    2. Bernardi, S. & Flammini, F. & Marrone, S. & Mazzocca, N. & Merseguer, J. & Nardone, R. & Vittorini, V., 2013. "Enabling the usage of UML in the verification of railway systems: The DAM-rail approach," Reliability Engineering and System Safety, Elsevier, vol. 120(C), pages 112-126.
    3. Kretzschmar, U. & Gomez-Cornejo, J. & Astarloa, A. & Bidarte, U. & Ser, J. Del, 2016. "Synchronization of faulty processors in coarse-grained TMR protected partially reconfigurable FPGA designs," Reliability Engineering and System Safety, Elsevier, vol. 151(C), pages 1-9.
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    Cited by:

    1. Ramezani, Reza & Ghavidel, Abolfazl & Sedaghat, Yasser, 2021. "Exact and efficient reliability and performance optimization of synchronous task graphs," Reliability Engineering and System Safety, Elsevier, vol. 205(C).
    2. Ramezani, Reza & Sedaghat, Yasser & Naghibzadeh, Mahmoud & Clemente, Juan Antonio, 2018. "A decomposition-based reliability and makespan optimization technique for hardware task graphs," Reliability Engineering and System Safety, Elsevier, vol. 180(C), pages 13-24.
    3. Jung, Seunghwa & Choi, Jihwan P., 2019. "Predicting system failure rates of SRAM-based FPGA on-board processors in space radiation environments," Reliability Engineering and System Safety, Elsevier, vol. 183(C), pages 374-386.
    4. Ramezani, Reza & Clemente, Juan Antonio & Franco, Francisco J., 2020. "Analytical reliability estimation of SRAM-based FPGA designs against single-bit and multiple-cell upsets," Reliability Engineering and System Safety, Elsevier, vol. 202(C).
    5. Hoque, Khaza Anuarul & Ait Mohamed, Otmane & Savaria, Yvon, 2019. "Dependability modeling and optimization of triple modular redundancy partitioning for SRAM-based FPGAs," Reliability Engineering and System Safety, Elsevier, vol. 182(C), pages 107-119.

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    More about this item

    Keywords

    SEU; FPGA; Emulation; Fault injection; FIT;
    All these keywords.

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