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Synchronization of faulty processors in coarse-grained TMR protected partially reconfigurable FPGA designs

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  • Kretzschmar, U.
  • Gomez-Cornejo, J.
  • Astarloa, A.
  • Bidarte, U.
  • Ser, J. Del

Abstract

The expansion of FPGA technology in numerous application fields is a fact. Single Event Effects (SEE) are a critical factor for the reliability of FPGA based systems. For this reason, a number of researches have been studying fault tolerance techniques to harden different elements of FPGA designs. Using Partial Reconfiguration (PR) in conjunction with Triple Modular Redundancy (TMR) is an emerging approach in recent publications dealing with the implementation of fault tolerant processors on SRAM-based FPGAs. While these works pay great attention to the repair of erroneous instances by means of reconfiguration, the essential step of synchronizing the repaired processors is insufficiently addressed. In this context, this paper poses four different synchronization approaches for soft core processors, which balance differently the trade-off between synchronization speed and hardware overhead. All approaches are assessed in practice by synchronizing TMR protected PicoBlaze processors implemented on a Virtex-5 FPGA. Nevertheless all methods are of a general nature and can be applied for different processor architectures in a straightforward fashion.

Suggested Citation

  • Kretzschmar, U. & Gomez-Cornejo, J. & Astarloa, A. & Bidarte, U. & Ser, J. Del, 2016. "Synchronization of faulty processors in coarse-grained TMR protected partially reconfigurable FPGA designs," Reliability Engineering and System Safety, Elsevier, vol. 151(C), pages 1-9.
    • Handle: RePEc:eee:reensy:v:151:y:2016:i:c:p:1-9
    DOI: 10.1016/j.ress.2015.12.018
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    References listed on IDEAS

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    1. Fort, Ada & Mugnaini, Marco & Vignoli, Valerio & Gaggii, Vittorio & Pieralli, Moreno, 2015. "Fault tolerant design of a field data modular readout architecture for railway applications," Reliability Engineering and System Safety, Elsevier, vol. 142(C), pages 456-462.
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    Cited by:

    1. Ramezani, Reza & Ghavidel, Abolfazl & Sedaghat, Yasser, 2021. "Exact and efficient reliability and performance optimization of synchronous task graphs," Reliability Engineering and System Safety, Elsevier, vol. 205(C).
    2. Yang, Shunkun & Shao, Qi & Bian, Chong, 2022. "Reliability analysis of ensemble fault tolerance for soft error mitigation against complex radiation effect," Reliability Engineering and System Safety, Elsevier, vol. 217(C).
    3. Villalta, Igor & Bidarte, Unai & Gómez-Cornejo, Julen & Jiménez, Jaime & Lázaro, Jesús, 2018. "SEU emulation in industrial SoCs combining microprocessor and FPGA," Reliability Engineering and System Safety, Elsevier, vol. 170(C), pages 53-63.
    4. Jung, Seunghwa & Choi, Jihwan P., 2019. "Predicting system failure rates of SRAM-based FPGA on-board processors in space radiation environments," Reliability Engineering and System Safety, Elsevier, vol. 183(C), pages 374-386.
    5. Hoque, Khaza Anuarul & Ait Mohamed, Otmane & Savaria, Yvon, 2019. "Dependability modeling and optimization of triple modular redundancy partitioning for SRAM-based FPGAs," Reliability Engineering and System Safety, Elsevier, vol. 182(C), pages 107-119.

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