Design and FPGA implementation of a high-speed PRNG based on an n-D non-degenerate chaotic system

Currently, low-dimensional chaotic maps have many disadvantages, such as narrow chaotic regions, numerous cycle windows, and weak chaotic representations. Based on this issue, an n-dimensional non-degenerate chaotic system (nD-NDCS) is constructed. By setting the control parameters of the system, we can obtain dimensionally adjustable non-degenerate chaotic systems with desired Lyapunov exponents. Compared with existing methods, the proposed nD-NDCS has a simple structure with few control parameters, which is suitable for resource-constrained scenarios, such as small embedded devices and mobile devices. To demonstrate the practicality of the proposed method, we construct a 3D-NDCS and a 4D-NDCS as two examples. Performance evaluations show better randomness and complexity than other methods in terms of sample entropy, permutation entropy and other indicators. Since both chaotic systems can produce pseudo-random sequences with sensitive initial values and strong randomness, we further design an efficient pseudo-random number generator (PRNG) on the FPGA. The experiment results show that the proposed PRNG occupies merely 3.13 % of the effective resources of the target FPGA. In addition, the throughput of the PRNG which obtained from post-processing is up to 15 Gb/s, and successfully passed the NIST SP800-22 test. Finally, an FPGA-based hardware implementation platform is developed to realize the proposed PRNG.