An Overview of the Decimation process and its VLSI implementation
Digital Decimation process plays an important task in communication system. It mostly is applied in transceiver when the frequency reduction is required. However, the decimation process for sigma delta modulator is considered in this research work. The proposed design was simulated using MATLAB software and implemented by hardware description language in Xilinx environment. Furthermore, the proposed advance arithmetic unit is applied to improve the system efficiency.
|Date of creation:||01 Feb 2006|
|Date of revision:||01 Feb 2006|
|Publication status:||Published in Research Student Seminar SPS2006 (2006): pp. 207-211|
|Contact details of provider:|| Postal: Ludwigstraße 33, D-80539 Munich, Germany|
Web page: https://mpra.ub.uni-muenchen.de
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