An Overview of the Decimation process and its VLSI implementation
Digital Decimation process plays an important task in communication system. It mostly is applied in transceiver when the frequency reduction is required. However, the decimation process for sigma delta modulator is considered in this research work. The proposed design was simulated using MATLAB software and implemented by hardware description language in Xilinx environment. Furthermore, the proposed advance arithmetic unit is applied to improve the system efficiency.
|Date of creation:||01 Feb 2006|
|Date of revision:||01 Feb 2006|
|Publication status:||Published in Research Student Seminar SPS2006 (2006): pp. 207-211|
|Contact details of provider:|| Postal: Ludwigstraße 33, D-80539 Munich, Germany|
Web page: https://mpra.ub.uni-muenchen.de
More information through EDIRC
When requesting a correction, please mention this item's handle: RePEc:pra:mprapa:41945. See general information about how to correct material in RePEc.
For technical questions regarding this item, or to correct its authors, title, abstract, bibliographic or download information, contact: (Joachim Winter)
If you have authored this item and are not yet registered with RePEc, we encourage you to do it here. This allows to link your profile to this item. It also allows you to accept potential citations to this item that we are uncertain about.
If references are entirely missing, you can add them using this form.
If the full references list an item that is present in RePEc, but the system did not link to it, you can help with this form.
If you know of missing items citing this one, you can help us creating those links by adding the relevant references in the same way as above, for each refering item. If you are a registered author of this item, you may also want to check the "citations" tab in your profile, as there may be some citations waiting for confirmation.
Please note that corrections may take a couple of weeks to filter through the various RePEc services.