Compact neuron circuit model with multiple neuromorphic behaviors: Design and dynamic analysis

Neuron circuits implemented in integrated circuits (IC) hold promise for large-scale neuromorphic computing but face two main limitations. One type employs simplified models lacking slow-variable regulation, preventing after-hyperpolarization (AHP) control and limiting the generation multiple neuromorphic behaviors. The other relies on abstract mathematical models, although these models can generate multiple behaviors, cannot be directly mapped to the I–V characteristics of MOSFETs. Therefore, circuits implemented in this design do not simulate biological characteristics and only perform mathematical operations, resulting in large area and high power consumption. Consequently, neither approach is suitable for large-scale, practical neuromorphic computing. To address these limitations, we design a novel neuron circuit model based on the variable transconductance of transistors across operating regions to mimic the time-varying conductance of ion channels without complex mathematical operations. Meanwhile, we construct an effective slow-variable regulation mechanism to realize the AHP process, thereby producing multiple neuromorphic behaviors. By reshaping the vector field and analyzing the equilibrium trajectory, we explain the nonlinear dynamical origins of multiple neuromorphic behaviors. The compact neuron circuit, implemented in 180 nm CMOS with only 10 transistors, consumes 100 pJ/spike and produces eight neuromorphic behaviors. Compared with existing designs, the proposed circuit offers significant advantages in area, power consumption, and dynamic behaviors.