Optimization of embedded cooling in 2.5D integrated circuits through genetic algorithm-driven TSV layout design

As chip performance advances, the accompanying increase in power consumption and heat generation presents significant challenges for effective thermal management. This paper undertakes a comprehensive investigation into the layout of through-silicon vias (TSVs) in 2.5D packaged chips and their effects on overall performance. A detailed model is developed, encompassing logic chips, memory chips, a silicon interposer, and a substrate, with deionized water employed as the coolant to simulate the thermal-mechanical coupling within the packaged chip. A genetic algorithm is utilized to optimize the arrangement of micropillars within microchannels. Notably, as the degrees of freedom increase, a reduction in peak temperature is observed. When the degrees of freedom reach 157, optimizing the horizontal and vertical coordinates, radius, and height of each TSV column as independent variables allows for finer adjustments, resulting in improved temperature uniformity. This study establishes a theoretical foundation and optimization methodology for the thermal design of 2.5D chips, thereby contributing to the development of more efficient and reliable thermal management solutions for future high-density integrated circuits.