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Feature-driven robust stochastic scheduling for printed circuit board assembly

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  • Li, Debiao
  • Ding, Ran
  • Liu, Feng
  • Wang, Ruiqi
  • Zhong, Yuanguang

Abstract

In printed circuit board assembly line scheduling, variability in machine performance and human intervention introduces significant uncertainty in processing and setup times, creating substantial challenges to achieving optimal schedules that impact customer satisfaction and production efficiency. This paper formulates the assembly process as identical parallel machines where both processing and setup times are uncertain, to minimize total completion time and makespan. We propose a feature-driven robust stochastic optimization model that leverages linear support vector regression to predict processing time and an event-wise ambiguity set derived from K-means clustering to capture setup time variability. The model is reformulated as a mixed-integer linear program and solved using a branch-and-price (B&P) algorithm for efficient optimization. Extensive computational experiments using real-world data from a global leading electronics manufacturer demonstrate that our model consistently outperforms sample average approximation (SAA) and standard distributionally robust optimization (DRO) models, achieving objective value improvements of 52% over the SAA model and 33% over the DRO model. The B&P algorithm efficiently solves realistically sized instances optimally within practical time limits. Based on the sensitivity analysis, the number of setup scenarios for scheduling settings significantly influences the tradeoff relationship between the solution accuracy and computational efficiency. This feature-driven optimization model has been successfully implemented in the electronics manufacturer since September 2022, enhancing throughput by 10.3% and achieving annual savings around 1.65 million US dollars.

Suggested Citation

  • Li, Debiao & Ding, Ran & Liu, Feng & Wang, Ruiqi & Zhong, Yuanguang, 2026. "Feature-driven robust stochastic scheduling for printed circuit board assembly," European Journal of Operational Research, Elsevier, vol. 334(2), pages 643-660.
  • Handle: RePEc:eee:ejores:v:334:y:2026:i:2:p:643-660
    DOI: 10.1016/j.ejor.2026.02.001
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