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Design and Analysis of 18 nm Graphene/TiO2/TiSix NMOS Device using Taguchi Method

Author

Listed:
  • Muhammad Fawwaz Aqil Ahmad Fairuz

    (Centre for Telecommunication Research and Innovation (CeTRI), Faculty of Technology and Engineering Electronic and Computer (FTKEK), Universiti Teknikal Malaysia Melaka (UteM), Hang Tuah Jaya, 76100 Durian Tunggal, Melaka, Malaysia)

  • Afifah Maheran Abdul Hamid

    (Centre for Telecommunication Research and Innovation (CeTRI), Faculty of Technology and Engineering Electronic and Computer (FTKEK), Universiti Teknikal Malaysia Melaka (UteM), Hang Tuah Jaya, 76100 Durian Tunggal, Melaka, Malaysia)

  • Pritigavane Mogan

    (Centre for Telecommunication Research and Innovation (CeTRI), Faculty of Technology and Engineering Electronic and Computer (FTKEK), Universiti Teknikal Malaysia Melaka (UteM), Hang Tuah Jaya, 76100 Durian Tunggal, Melaka, Malaysia)

  • Nur Fathia ‘Azizi

    (Centre for Telecommunication Research and Innovation (CeTRI), Faculty of Technology and Engineering Electronic and Computer (FTKEK), Universiti Teknikal Malaysia Melaka (UteM), Hang Tuah Jaya, 76100 Durian Tunggal, Melaka, Malaysia)

  • Nur Hazwani Naili Mohd Nizam

    (Faculty of Technology and Applied Science, Innovative University College, Jalan SS7/26, 47301 Petaling Jaya, Selangor, Malaysia)

  • Fauziyah Salehuddin

    (Centre for Telecommunication Research and Innovation (CeTRI), Faculty of Technology and Engineering Electronic and Computer (FTKEK), Universiti Teknikal Malaysia Melaka (UteM), Hang Tuah Jaya, 76100 Durian Tunggal, Melaka, Malaysia)

  • Khairil Ezwan Kaharudin

    (Faculty of Engineering and Built Environment, Lincoln University College, Jalan SS 7/15, 47301 Petaling Jaya, Selangor, Malaysia.)

Abstract

Metal Oxide Semiconductor Field Effect Transistor (MOSFET) has been steady growth in high-speed switching applications in the semiconductor industry. The conventional combination of regular has to be replaced with high-k materials due to the limitation of shrinking the transistors. In this paper, Silicon Dioxide (SiO2) and Polysilicon gate structure has been replaced with high-k materials and metal gate which are Titanium Dioxide (TiO2) and Titanium Silicide (TiSix) respectively. The main objectives of this project are to reduce the leakage current (IOFF) and optimum threshold voltage (VTH) for the NMOS device. The designed and analyzed NMOS will be demonstrated in Silvaco software with ATHENA as a virtual fabrication process and ATLAS as analyzing the electric properties of the device. The results have been analyzed using Taguchi L9 orthogonal array method to obtain nominal values of threshold voltage and minimum value of leakage current. The initial results before optimizing with the Taguchi Method are 0.500061 V for VTH and 13.2042 pA/μm for IOFF. Once the device is optimized with Taguchi Method, the optimum value for VTH is 0.540576 V and 12.9181 pA/μm for IOFF. These values are met with the targeted values based on International Technology Roadmap for Semiconductors (ITRS) projection.

Suggested Citation

  • Muhammad Fawwaz Aqil Ahmad Fairuz & Afifah Maheran Abdul Hamid & Pritigavane Mogan & Nur Fathia ‘Azizi & Nur Hazwani Naili Mohd Nizam & Fauziyah Salehuddin & Khairil Ezwan Kaharudin, 2025. "Design and Analysis of 18 nm Graphene/TiO2/TiSix NMOS Device using Taguchi Method," International Journal of Research and Innovation in Social Science, International Journal of Research and Innovation in Social Science (IJRISS), vol. 9(9), pages 8794-8803, September.
    • Handle: RePEc:bcp:journl:v:9:y:2025:issue-9:p:8794-8803
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