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Design and realization On Board Data Handling for remote sensing payload of nanosatellite FPGA base

Listed author(s):
  • Cahyono, Dwi
  • Nugroho, Arifin
  • Hidayat, Iswahyudi
Registered author(s):

    The electronics and materials technology over the past decade provide new breakthroughs in the development of ICT (Information and Communication Technology) field one is on satellite technology. Currently ,satellite has been getting development in miniaturizing dimension and components to the level of 1 kg weight. Nanosatellite is a class of satellites less than 10 kg in weight. One of the component subsystems that are in remote sensing payload nanosatellite which is contained within OBC (On-Board Computer) and in the application called OBDH (On Board Data Handling). The presence of the platform OBDH nanosatellite payload subsystem is very important, because to serve the flow of data from the camera and the transmitter. In this project, it will be designed and realized OBDH-based on FPGA (Field Programmable Gate Array). Because FPGA has many advantages over commonly used conventional microcontroller. In the development of space technology implementation for FPGA resistant to radiation effects in a parallel mechanism in the internal system that is ideal for future space applications, higher computational capability, low power consumption, small hardware size, and many others. FPGA-based OBDH in this thesis are designed to set the process and control bits data input from the camera to the SDRAM and to the transmitter output from the SDRAM to be sent to the Ground Segment. Components are required as input the output information in the form of camera payload TCM 8240MD, internal SDRAM FPGA board. Communication used between the camera and FPGA with I2C bus protocol (Inter-IC). This FPGA will be encoded in VHDL language. Software used in a VHDL design is WebPack XILINX ISE, ModelSim, XSTOOLs Utilities. The execution and realization will be conducted in the supporters laboratory such as Digital Techniques and Microprocessor and Interfacing Laboratory. FPGA used is a Xilinx Spartan-200A XuLA with a maximum operating frequency of 384 MHz, because of the small dimension and the low power consumption and digital camera 1.3 Megapixels TCM 8240 that is capable with the Xula200 for performance in imaging. Going forward, the algorithm is programmed with VHDL language will be generated into the ASIC to strengthen and make it solid logic gates in the VHDL language in future space technology research.

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    Paper provided by International Telecommunications Society (ITS) in its series 19th ITS Biennial Conference, Bangkok 2012: Moving Forward with Future Technologies - Opening a Platform for All with number 72481.

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    Date of creation: 2012
    Handle: RePEc:zbw:itsb12:72481
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