Derating Design of Control Circuits Based on Harpness Simulation

Derating design, as a classical and extensively applied method in circuit reliability engineering, plays a pivotal role in maintaining the stable performance of electronic circuits. Nevertheless, traditional derating methodologies are limited by several challenges, including a high degree of subjectivity, the absence of standardized quantitative criteria, computational complexity, and significant difficulty in accurately assessing transient electrical stresses during component evaluation. To overcome these limitations, this study incorporates the simulation analysis module of Harpness software to enhance the derating design process. By utilizing simulation-based calculations of electrical stress under both standard operating conditions and extreme scenarios, the proposed approach facilitates precise assessment of transient electrical stresses and component junction temperatures. The simulation platform outputs data tables that provide detailed stress analysis and derating evaluations for all components, thereby substantially improving the accuracy and efficiency of the derating design process. Particular attention is given to the simulation methodology for FPGA device derating, which applies equivalent circuit 1 odelling and equivalent load techniques to enable accurate simulation analysis.