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Hierarchical Modeling for Monitoring Defects

In: Frontiers in Statistical Quality Control 9

Author

Listed:
  • Christina M. Mastrangelo

    (University of Washington)

  • Naveen Kumar

    (Intel Hillsboro)

  • David Forrest

    (Virginia Institute of Marine Science)

Abstract

Summary In semiconductor manufacturing, discovering the processes that are attributable to defect rates is a lengthy and expensive procedure. This paper proposes a approach for understanding the impact of process variables on defect rates. By using a process-based hierarchical model, we can relate sub-process manufacturing data to layer-specific defect rates. This paper demonstrates a hierarchical modeling method using process data drawn from the Gate Contact layer, Metal 1 layer, and Electrical Test data to produce estimates of defect rates. A benefit of the hierarchical approach is that the parameters of the high-level model may be interpreted as the relative contributions of the sub-models to the overall yield. Additionally, the output from the sub-models may be monitored with a control chart that is ‘oriented’ toward yield.

Suggested Citation

  • Christina M. Mastrangelo & Naveen Kumar & David Forrest, 2010. "Hierarchical Modeling for Monitoring Defects," Springer Books, in: Hans-Joachim Lenz & Peter-Theodor Wilrich & Wolfgang Schmid (ed.), Frontiers in Statistical Quality Control 9, pages 225-236, Springer.
    • Handle: RePEc:spr:sprchp:978-3-7908-2380-6_15
    DOI: 10.1007/978-3-7908-2380-6_15
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