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Pseudo-Vectorization and RISC Optimization Techniques for the Hitachi SR8000 Architecture

In: High Performance Computing in Science and Engineering, Munich 2002

Author

Listed:
  • Georg Hager

    (Regionales Rechenzentrum Erlangen)

  • Frank Deserno

    (Regionales Rechenzentrum Erlangen)

  • Gerhard Wellein

    (Regionales Rechenzentrum Erlangen)

Abstract

We demonstrate optimization techniques for the Hitachi SR8000 architecture on CPU and SMP level using selected case studies from real-world codes. Special emphasis is given to a comparison with performance characteristics of other modern RISC and vector CPUs.

Suggested Citation

  • Georg Hager & Frank Deserno & Gerhard Wellein, 2003. "Pseudo-Vectorization and RISC Optimization Techniques for the Hitachi SR8000 Architecture," Springer Books, in: Siegfried Wagner & Arndt Bode & Werner Hanke & Franz Durst (ed.), High Performance Computing in Science and Engineering, Munich 2002, pages 425-442, Springer.
    • Handle: RePEc:spr:sprchp:978-3-642-55526-8_34
    DOI: 10.1007/978-3-642-55526-8_34
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