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Exploring a Design Space of 3-D Stacked Vector Processors

In: Sustained Simulation Performance 2012

Author

Listed:
  • Ryusuke Egawa

    (Tohoku University/JST CREST, Cyberscience Center)

  • Jubee Tada

    (Yamagata University, Graduate School of Science and Engineering)

  • Hiroaki Kobayashi

    (Tohoku University/JST CREST, Cyberscience Center)

Abstract

Three dimensional (3-D) technologies have come under the spotlight to overcome limitations of conventional two dimensional (2-D) microprocessor implementations. However, the effect of 3-D integrations with vertical interconnects in future vector processors design is not well discussed yet. In this paper, aiming at exploring the design space of future vector processors, fine and coarse grain 3-D integrations that aggressively employ vertical interconnects are designed and evaluated.

Suggested Citation

  • Ryusuke Egawa & Jubee Tada & Hiroaki Kobayashi, 2013. "Exploring a Design Space of 3-D Stacked Vector Processors," Springer Books, in: Michael M. Resch & Xin Wang & Wolfgang Bez & Erich Focht & Hiroaki Kobayashi (ed.), Sustained Simulation Performance 2012, edition 127, pages 35-49, Springer.
    • Handle: RePEc:spr:sprchp:978-3-642-32454-3_4
    DOI: 10.1007/978-3-642-32454-3_4
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