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Complexities of Performance Prediction for Bandwidth-Limited Loop Kernels on Multi-Core Architectures

In: High Performance Computing in Science and Engineering, Garching/Munich 2009

Author

Listed:
  • Jan Treibig

    (Friedrich-Alexander Universität Erlangen-Nürnberg, Regionales Rechenzentrum Erlangen)

  • Georg Hager

    (Friedrich-Alexander Universität Erlangen-Nürnberg, Regionales Rechenzentrum Erlangen)

  • Gerhard Wellein

    (Friedrich-Alexander Universität Erlangen-Nürnberg, Regionales Rechenzentrum Erlangen)

Abstract

The balance metric is a simple approach to estimate the performance of bandwidth-limited loop kernels. However, applying the method to modern multi-core architectures yields unsatisfactory results. This paper analyzes the influence of cache hierarchy design on performance predictions for bandwidth-limited loop kernels on current mainstream processors. We present a diagnostic model with improved predictive power, correcting the limitations of the simple balance metric. The importance of code execution overhead even in bandwidth-bound situations is emphasized.

Suggested Citation

  • Jan Treibig & Georg Hager & Gerhard Wellein, 2010. "Complexities of Performance Prediction for Bandwidth-Limited Loop Kernels on Multi-Core Architectures," Springer Books, in: Siegfried Wagner & Matthias Steinmetz & Arndt Bode & Markus Michael Müller (ed.), High Performance Computing in Science and Engineering, Garching/Munich 2009, pages 3-12, Springer.
    • Handle: RePEc:spr:sprchp:978-3-642-13872-0_1
    DOI: 10.1007/978-3-642-13872-0_1
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