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Lessons Learned from 1-Year Experience with SX-9 and Toward the Next Generation Vector Computing

In: High Performance Computing on Vector Systems 2009

Author

Listed:
  • Hiroaki Kobayashi

    (Tohoku University)

  • Ryusuke Egawa

    (Tohoku University)

  • Hiroyuki Takizawa

    (Tohoku University)

  • Koki Okabe

    (Tohoku University)

  • Akihiko Musa

    (Tohoku University
    NEC Corporation)

  • Takashi Soga

    (Tohoku University
    NEC System Technologies)

  • Yoko Isobe

    (NEC Computertehno, Ltd.)

Abstract

This paper discusses the performance of the latest vector-parallel supercomputer system SX-9. First, we report HPC challenge benchmark results of the SX-9 system, in which it achieves 19 top one scores in the 28 tests. In addition, we also discuss some tuning techniques for SX-9. We present case study analysis, in which the effects of code tuning for ADB, a newly introduced, software-controllable on chip cache of SX-9, on the sustained performance is examined by using science and engineering applications. Finally, we present our on-going research work on design of a multi-vector core processor toward the next generation vector computing. Through the experimental results, we confirm that vector caching plays an important role to extract the potential of the multi-vector core processor.

Suggested Citation

  • Hiroaki Kobayashi & Ryusuke Egawa & Hiroyuki Takizawa & Koki Okabe & Akihiko Musa & Takashi Soga & Yoko Isobe, 2010. "Lessons Learned from 1-Year Experience with SX-9 and Toward the Next Generation Vector Computing," Springer Books, in: Michael Resch & Sabine Roller & Katharina Benkert & Martin Galle & Wolfgang Bez & Hiroaki Kobayashi (ed.), High Performance Computing on Vector Systems 2009, pages 3-22, Springer.
    • Handle: RePEc:spr:sprchp:978-3-642-03913-3_1
    DOI: 10.1007/978-3-642-03913-3_1
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