FEAST: Development of HPC Technologies for FEM Applications

Modern processors reach their performance speedup not merely by increasing clock frequency, but to a greater extend by fundamental changes and extensions of the processor architecture itself. These extensions require the application developer to adapt programming techniques to exploit the existing performance potential. Otherwise the situation may arise that the processor becomes nominally faster, but the application doesn’t run faster [3, 4]. A limiting factor for computations is memory access. There is an ever increasing discrepancy between CPU cycle time and main storage access time. Fetching data is expensive in terms of CPU being idle. To narrow the gap between smaller CPU cycle times and possible access times of main storage in general, a rapid access temporary storage between CPU and main storage was introduced, the so-called cache. The basic idea of a cache is to store data following the locality of reference principle. Latency is reduced if a subsequently requested datum is found in the faster cache instead of having to transfer it from slow main storage. Given a sufficient locality of the data, i.e. the data of preceding accesses is still cached, the number of accesses to the cache will exceed those to slow main storage. Throughput can be increased significantly this way. Access to main storage will not be faster with any access sample automatically, but only if the program uses mainly data being already in the cache. This requires appropriate adjustments being made to the applications [2].