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The Potential of On-Chip Memory Systems for Future Vector Architectures

In: High Performance Computing on Vector Systems 2007

Author

Listed:
  • Hiroaki Kobayashi

    (Tohoku University, Information Synergy Center
    Tohoku University, Graduate School of Information Sciences)

  • Akihiko Musa

    (Tohoku University, Graduate School of Information Sciences
    NEC Corporation)

  • Yoshiei Sato

    (Tohoku University, Graduate School of Information Sciences)

  • Hiroyuki Takizawa

    (Tohoku University, Information Synergy Center
    Tohoku University, Graduate School of Information Sciences)

  • Koki Okabe

    (Tohoku University, Information Synergy Center)

Abstract

The most advantageous feature of modern vector systems is their outstanding memory performance compared to scalar systems. This feature brings them to their high-sustained system performance when executing real application codes, which are extensively used in the fields of advanced sciences and engineering [9],[10],[1]. However, recent trends in semiconductor technology generate a strong head wind for vector systems. Thanks to the historical growth rate in on-chip silicon budget, named Moore’s law, processor performance regarding flop/s rates increases remarkably, but memory performance cannot follow it [2]. Regarding vector systems, their bytes/flop rates that show the balance between flop/s performance and memory bandwidth go down from 8 B/flop in 1998, to 4 in 2003, and to 2 in 2007. We have pointed out that reducing the memory bandwidth seriously affects the sustained system performance even in case of vector systems [3], although their absolute performance increases to a certain degree. Memory performance definitely becomes one of key points for design of future highly-efficient vector architectures to survive in an era of multi-core processors.

Suggested Citation

  • Hiroaki Kobayashi & Akihiko Musa & Yoshiei Sato & Hiroyuki Takizawa & Koki Okabe, 2008. "The Potential of On-Chip Memory Systems for Future Vector Architectures," Springer Books, in: Michael Resch & Sabine Roller & Peter Lammers & Toshiyuki Furui & Martin Galle & Wolfgang Bez (ed.), High Performance Computing on Vector Systems 2007, pages 247-264, Springer.
    • Handle: RePEc:spr:sprchp:978-3-540-74384-2_18
    DOI: 10.1007/978-3-540-74384-2_18
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