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Challenges and Potentials of Emerging Multicore Architectures

In: High Performance Computing in Science and Engineering, Garching/Munich 2007

Author

Listed:
  • Markus Stürmer

    (Universität Erlangen-Nürnberg, Lehrstuhl f. Systemsimulation)

  • Gerhard Wellein

    (Regionales Rechenzentrum Erlangen)

  • Georg Hager

    (Regionales Rechenzentrum Erlangen)

  • Harald Köstler

    (Universität Erlangen-Nürnberg, Lehrstuhl f. Systemsimulation)

  • Ulrich Rüde

    (Universität Erlangen-Nürnberg, Lehrstuhl f. Systemsimulation)

Abstract

We present performance results on two current multicore architectures, a STI (Sony, Toshiba, and IBM) Cell processor included in the new Playstation™ 3 and a Sun UltraSPARC T2 (“Niagara 2”) machine. On the Niagara 2 we analyze typical performance patterns that emerge from the peculiar way the memory controllers are activated on this chip using the standard STREAM benchmark and a shared-memory parallel lattice Boltzmann code. On the Cell processor we measure the memory bandwidth and run performance tests for LBM simulations. Additionally, we show results for an application in image processing on the Cell processor, where it is required to solve nonlinear anisotropic PDEs.

Suggested Citation

  • Markus Stürmer & Gerhard Wellein & Georg Hager & Harald Köstler & Ulrich Rüde, 2009. "Challenges and Potentials of Emerging Multicore Architectures," Springer Books, in: Siegfried Wagner & Matthias Steinmetz & Arndt Bode & Matthias Brehm (ed.), High Performance Computing in Science and Engineering, Garching/Munich 2007, pages 551-566, Springer.
    • Handle: RePEc:spr:sprchp:978-3-540-69182-2_43
    DOI: 10.1007/978-3-540-69182-2_43
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