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Evaluating Out-of-Order Engine Limitations Using Uop Flow Simulation

In: Tools for High Performance Computing 2015

Author

Listed:
  • Vincent Palomares

    (University of Versailles Saint-Quentin-en-Yvelines)

  • David C. Wong

    (Intel Corporation)

  • David J. Kuck

    (Intel Corporation)

  • William Jalby

    (University of Versailles Saint-Quentin-en-Yvelines)

Abstract

Out-of-order mechanisms in recent microarchitectures do a very good job at hiding latencies and improving performance. However, they come with limitations not easily modeled statically, and hard to quantify exactly even dynamically. This paper will present Uop Flow Simulation (UFS), a loop performance prediction technique accounting for such restrictions by combining static analysis and cycle-driven simulation. UFS simulates the behavior of the execution pipeline when executing a loop. It handles instruction latencies, dependencies, out-of-order resource consumption and other low-level details while completely ignoring semantics. We will use a UFS prototype to validate our approach on Sandy Bridge using loops from real-world HPC applications, showing it is both accurate and very fast (reaching simulation speeds of hundreds of thousands of cycles per second).

Suggested Citation

  • Vincent Palomares & David C. Wong & David J. Kuck & William Jalby, 2016. "Evaluating Out-of-Order Engine Limitations Using Uop Flow Simulation," Springer Books, in: Andreas Knüpfer & Tobias Hilbrich & Christoph Niethammer & José Gracia & Wolfgang E. Nagel & Michael (ed.), Tools for High Performance Computing 2015, chapter 0, pages 161-181, Springer.
    • Handle: RePEc:spr:sprchp:978-3-319-39589-0_13
    DOI: 10.1007/978-3-319-39589-0_13
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