Interconnection Network: Design Space Exploration of Network for Supercomputers

This chapter reports design space exploration for an interconnection network subsystem in a supercomputer targeting memory-intensive applications, which had been conducted in a feasibility study for the next-generation supercomputers. Supercomputers composed of many nodes with high-performance processors also require a high performance network so that computing performance can be scaled up to the entire system. In our design space exploration, we discuss feasibility of networks with various topologies based on 64 × 64 high-radix crossbar switches with the assumption of a system overview and available technologies by 2018. Preliminary evaluation suggests that a full fat tree network and a fat-tree-torus hybrid network are promising in terms of a network diameter and the number of links, in comparison with the other topologies including a 3D or 5D torus and a dragonfly. In detailed evaluation, we estimate communication performance, cost, and power consumption for the two promising networks. The obtained results show that the hybrid network can have shorter latency for local point-to-point communication than the full fat tree network while both the networks can have comparable performance for collective communications.