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Model-Based Variation-Aware Integrated Circuit Design

In: Surrogate-Based Modeling and Optimization

Author

Listed:
  • Ting Zhu

    (North Carolina State University, Department of Electrical and Computer Engineering)

  • Mustafa Berke Yelten

    (North Carolina State University, Department of Electrical and Computer Engineering)

  • Michael B. Steer

    (North Carolina State University, Department of Electrical and Computer Engineering)

  • Paul D. Franzon

    (North Carolina State University, Department of Electrical and Computer Engineering)

Abstract

Modern integrated circuit designers must deal with complex design and simulation problems while coping with large device to device parametric variations and often imperfect information. This chapter presents surrogate model-based methods to generate circuit performance models for design, device models, and high-speed input-output (IO) buffer macromodels. Circuit performance models are built with design parameters and parametric variations, and they can be used for fast and systematic design space exploration and yield analysis. Surrogate models of the main device characteristics are generated in order to assess the effects of variability in analog circuits. The variation-aware IO buffer macromodel integrates surrogate modeling and a physically based model structure. The new IO macromodel provides both good accuracy and scalability for signal integrity analysis.

Suggested Citation

  • Ting Zhu & Mustafa Berke Yelten & Michael B. Steer & Paul D. Franzon, 2013. "Model-Based Variation-Aware Integrated Circuit Design," Springer Books, in: Slawomir Koziel & Leifur Leifsson (ed.), Surrogate-Based Modeling and Optimization, edition 127, pages 171-188, Springer.
    • Handle: RePEc:spr:sprchp:978-1-4614-7551-4_8
    DOI: 10.1007/978-1-4614-7551-4_8
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