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Layered CHIPS Instruments and Firm Response: Evidence from Micron’s High Bandwidth Memory Investment Program

In: Proceedings of the 2026 11th International Conference on Financial Innovation and Economic Development (ICFIED 2026)

Author

Listed:
  • Chi Zhang

    (Santa Monica College)

Abstract

This article examines how the United States’ layered industrial policies—the Chip Manufacturing and Manufacturing Information System (CHIPS) incentive, Sect. 48D Advanced Manufacturing Investment Credit, and New York State’s performance-based program—influenced Micron’s investment in high-bandwidth memory (HBM). The study assesses attachment, conditionality, and governance mechanisms by tracking the flow of key disclosures (2022–2025). Evidence suggests that these policy instruments reinforce each other: CHIPS anchors location and timing; Sect. 48D enhances after-tax returns; and New York State adds milestone projects and community benefit obligations backed by state capacity. Governance mechanisms—milestone project expenditures, recaptures, and foreign entity guardrails—redistribute bargaining power, curb subsidy leakage, and shift execution risk toward on-time delivery. Policy effects are expected to propagate through system bottlenecks, expand domestic HBM supply, and pave the way for advanced packaging readiness, although capacity remains a limiting factor. Remaining risks relate to execution capacity, workforce, and policy durability.

Suggested Citation

  • Chi Zhang, 2026. "Layered CHIPS Instruments and Firm Response: Evidence from Micron’s High Bandwidth Memory Investment Program," Advances in Economics, Business and Management Research, in: Xiongfeng Pan & Huaping Sun & Abdul Rauf & Md Rabiul Islam & Liew Chee Yoong (ed.), Proceedings of the 2026 11th International Conference on Financial Innovation and Economic Development (ICFIED 2026), pages 579-587, Springer.
    • Handle: RePEc:spr:advbcp:978-94-6239-642-5_56
    DOI: 10.2991/978-94-6239-642-5_56
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