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Groebner Bases Based Verification Solution for SystemVerilog Concurrent Assertions

Author

Listed:
  • Ning Zhou
  • Xinyan Gao
  • Jinzhao Wu
  • Jianchao Wei
  • Dakui Li

Abstract

We introduce an approach exploiting the power of polynomial ring algebra to perform SystemVerilog assertion verification over digital circuit systems. This method is based on Groebner bases theory and sequential properties checking. We define a constrained subset of SVAs so that an efficient polynomial modeling mechanism for both circuit descriptions and assertions can be applied. We present an algorithm framework based on the algebraic representations using Groebner bases for concurrent SVAs checking. Case studies show that computer algebra can provide canonical symbolic representations for both assertions and circuit designs and can act as a novel solver engine from the viewpoint of symbolic computation.

Suggested Citation

  • Ning Zhou & Xinyan Gao & Jinzhao Wu & Jianchao Wei & Dakui Li, 2014. "Groebner Bases Based Verification Solution for SystemVerilog Concurrent Assertions," Journal of Applied Mathematics, John Wiley & Sons, vol. 2014(1).
  • Handle: RePEc:wly:jnljam:v:2014:y:2014:i:1:n:194574
    DOI: 10.1155/2014/194574
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    References listed on IDEAS

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    1. Ning Zhou & Jinzhao Wu & Xinyan Gao, 2013. "Algebraic Verification Method for SEREs Properties via Groebner Bases Approaches," Journal of Applied Mathematics, Hindawi, vol. 2013, pages 1-10, April.
    2. Ning Zhou & Jinzhao Wu & Xinyan Gao, 2013. "Algebraic Verification Method for SEREs Properties via Groebner Bases Approaches," Journal of Applied Mathematics, John Wiley & Sons, vol. 2013(1).
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