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The design of a configurable and low-latency packet parsing system for communication networks

Author

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  • Kai-Sheng Hsu

    (National Taiwan University of Science and Technology)

  • Chung-An Shen

    (National Taiwan University of Science and Technology)

Abstract

Parsing is a critical packet processing function in the network node, and the performance and configurability of the packet parsing is essential for designing a low-latency and highly flexible network. This paper presents the VLSI architecture design and circuit implementation of a configurable and low-latency packet parser. The proposed packet parser is based on an instruction architecture to achieve configurability. Furthermore, a novel instruction-reusing scheme is employed in the packet parser so that the instruction-fetch operation is minimized and the latency is reduced. Moreover, in order to reduce size of the required memory, a new structure for the instruction memory is designed where multiple instructions share the same memory location. The proposed packet parser is designed and implemented with a ASIC design flow as well as based on the FPGA platform. Performance evaluations based on the post-layout simulation shows that the proposed packet parser reduces the latency by 30% and the required memory by 70%for the IPv4 and IPv6 protocols.

Suggested Citation

  • Kai-Sheng Hsu & Chung-An Shen, 2023. "The design of a configurable and low-latency packet parsing system for communication networks," Telecommunication Systems: Modelling, Analysis, Design and Management, Springer, vol. 82(4), pages 451-463, April.
    • Handle: RePEc:spr:telsys:v:82:y:2023:i:4:d:10.1007_s11235-023-00992-9
    DOI: 10.1007/s11235-023-00992-9
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