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Adaptive Multimodule Routers for Multiprocessor Architectures

Author

Listed:
  • Suresh Chalasani

    (University of Wisconsin-Parkside)

  • Rajendra V. Boppana

    (The Univ. of Texas at San Antonio)

Abstract

Recent multiprocessors such as Cray T3D support interprocessor communication using partitioned dimension-order routers (PDRs). In a PDR implementation, the routing logic and switching hardware is partitioned into multiple modules, with each module suitable for implementation as a chip. This paper proposes a method to incorporate adaptivity into such routers with simple changes to the router structure and logic. We show that with as few as two virtual channels per physical channel, adaptivity can be provided to handle nonuniform traffic in multidimensional meshes.

Suggested Citation

  • Suresh Chalasani & Rajendra V. Boppana, 2005. "Adaptive Multimodule Routers for Multiprocessor Architectures," Information Systems Frontiers, Springer, vol. 7(3), pages 317-327, July.
  • Handle: RePEc:spr:infosf:v:7:y:2005:i:3:d:10.1007_s10796-005-2772-5
    DOI: 10.1007/s10796-005-2772-5
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    Cited by:

    1. Chulhwan Chris Bang, 2015. "Information systems frontiers: Keyword analysis and classification," Information Systems Frontiers, Springer, vol. 17(1), pages 217-237, February.

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