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Performance analysis of 1D-to-2D array conversion for priority encoders in post-layout design

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  • Dhandapani Vaithiyanathan

    (National Institute of Technology Delhi)

  • Abhishek Behera

    (National Institute of Technology Delhi)

  • Alok Kumar Mishra

    (National Institute of Technology Delhi)

  • Preeti Verma

    (National Institute of Technology Delhi)

Abstract

This paper presents post-layout analysis of a modified 64-bit Priority Encoder (PE) design optimized for speed and efficiency. Our previous research implemented a scalable 1D-to-2D array conversion technique for PE implementation, demonstrating its effectiveness in 4-bit, 16-bit, and 64-bit designs. Here, we extend this approach by analyzing the post-layout performance of a 1V 64-bit PE fabricated in an 180 nm CMOS process. Compared to a reference design, our post-layout simulations reveal a significant 47.37% improvement in operating frequency. This remarkable enhancement highlights the robustness and efficiency of our proposed PE architecture, making it particularly suitable for high-speed data processing applications.

Suggested Citation

  • Dhandapani Vaithiyanathan & Abhishek Behera & Alok Kumar Mishra & Preeti Verma, 2025. "Performance analysis of 1D-to-2D array conversion for priority encoders in post-layout design," International Journal of System Assurance Engineering and Management, Springer;The Society for Reliability, Engineering Quality and Operations Management (SREQOM),India, and Division of Operation and Maintenance, Lulea University of Technology, Sweden, vol. 16(10), pages 3430-3439, October.
    • Handle: RePEc:spr:ijsaem:v:16:y:2025:i:10:d:10.1007_s13198-025-02868-4
    DOI: 10.1007/s13198-025-02868-4
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