1-bit full adder design using next generation semiconductor devices and performance benchmarking at low supply voltages

Due to scaling down the process in VLSI technology, MOSFET faces operational problems like short channel effect and design issues like increased gate-oxide leakage, junction leakage, high sub-threshold conduction, lower output impedance, and self-heating. Due to these design issues, there are some limitations, and a significant challenge is power consumption. To overcome the current obstacle for optimizing the innovations, the next-generation semiconductive materials of FinFET and other technological advancements are taken to implement the designs. The second-order limitations and most primarily causing threats are possibly avoided by choosing these semiconductor transistors. Two types of latest and currently used technological nodes are taken to implement the adder modules to prove and structure the developments. Full adder performs all the arithmetic operations. It is designed using the GDI technique, a gate diffusion input technique. Usage of this technique reduces the number of transistors, and transistors easily switch from OFF to ON and vice versa. To analyze and evaluate the proposed work, the standard elevation specifications of commonly used features are considered to give the circuits merits and limitations.