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Architectural analysis of 1-D to 2-D array conversion of priority encoder

Author

Listed:
  • Alok Kumar Mishra

    (National Institute of Technology Delhi)

  • Shail Anand

    (National Institute of Technology Delhi)

  • Nishant Singh

    (National Institute of Technology Delhi)

  • Vaithiyanathan Dhandapani

    (National Institute of Technology Delhi)

  • Baljit Kaur

    (National Institute of Technology Delhi)

Abstract

In this paper, a high-performance priority encoder of the 2-dimensional array is investigated and modified. This work involves 64-bit priority encoder design and verification using Verilog and cadence virtuoso. For the Verilog code, Vivado has been used for the Artix-7 FPGA board. For Cadence virtuoso, GPDK 180 nm CMOS technology has been used. By using a reduced 2-D priority encoder, 1000 transistors have been saved. Due to this, the delay of the whole 64-bit priority encoder is reduced by 62.17% as compared to PE64 and 61.68% as compared to modified PE64.

Suggested Citation

  • Alok Kumar Mishra & Shail Anand & Nishant Singh & Vaithiyanathan Dhandapani & Baljit Kaur, 2023. "Architectural analysis of 1-D to 2-D array conversion of priority encoder," International Journal of System Assurance Engineering and Management, Springer;The Society for Reliability, Engineering Quality and Operations Management (SREQOM),India, and Division of Operation and Maintenance, Lulea University of Technology, Sweden, vol. 14(5), pages 1726-1737, October.
    • Handle: RePEc:spr:ijsaem:v:14:y:2023:i:5:d:10.1007_s13198-023-01977-2
    DOI: 10.1007/s13198-023-01977-2
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