Leveraging controllability measures for high transition delay test coverage in DTESFF based partial enhanced scan design

Scan design is extensively exploited to test transition delay faults (TDF). Broadside test commonly referred as launch on capture and skewed load test is also commonly referred as launch-on-shift are two approaches to test TDF’s through scan design. However arbitrary test vector pair application is not supported by scan design because of architectural constraint of scan and this eventually limits the fault coverage for TDFs. Arbitrary test vector application is supported in enhanced scan design which alleviates the problem of poor fault coverage. Enhanced scan design has high area overhead and this problem can be further tackled through interchanging extra flip-flop by hold latch in enhanced scan. However hold signal required in enhanced scan design consists of hold latch is fast in nature. This signal is exactly equivalent of scan enable signal in skewed load test. Enhanced scan cell using one clock cycle slower hold signal is implemented in delay testable enhanced scan flip-flop (DTESFF) design. Partial enhanced scan method based on DTESFF design by using controllability measures for scan flip-flop identification is proposed for high transition delay test coverage in this work. Simulation results demonstrate the test coverage improvement for TDF in ISCAS 89 benchmark circuits.