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Estimating Spurious Power While Mapping K-Lut-Based Fpga Circuits

Author

Listed:
  • Ion Bucur

    () (University Politehnica of Bucharest)

  • Nicolae Cupcea

    () (University Politehnica of Bucharest)

  • Adrian Surpateanu

    () (University Politehnica of Bucharest)

  • Cornel Popescu

    () (University Politehnica of Bucharest)

Abstract

In this paper is presented a new approach for decreasing the spurious power consumption in K-LUT based FPGA implemented circuits. The approach is based on selective collapsing nodes in a direct acyclic graph (DAG) representing combinational or synchronous sequential circuits. It was used the simulation-based approach that estimates, using Monte Carlo experiment, the spurious switching activity of each net in the circuit. Traversing circuits in topological order, step by step best K-feasible cone are computed at the output of each node. Preserving the best depth of the circuits the mapping stage is done searching to minimize spurious switching power.

Suggested Citation

  • Ion Bucur & Nicolae Cupcea & Adrian Surpateanu & Cornel Popescu, 2009. "Estimating Spurious Power While Mapping K-Lut-Based Fpga Circuits," Journal of Information Systems & Operations Management, Romanian-American University, vol. 3(2), pages 388-397, December.
  • Handle: RePEc:rau:jisomg:v:3:y:2009:i:2:p:388-397
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