Optimal Area And Performance Mapping Of K-Lut Based Fpgas
FPGA circuits are increasingly used in many fields: for rapid prototyping of new products (including fast ASIC implementation), for logic emulation, for producing a small number of a device, or if a device should be reconfigurable in use (reconfigurable computing). Determining if an arbitrary, given wide, function can be implemented by a programmable logic block, unfortunately, it is generally, a very difficult problem. This problem is called the Boolean matching problem. This paper introduces a new implemented algorithm able to map, both for area and performance, combinational networks using k-LUT based FPGAs.
Volume (Year): 2 (2008)
Issue (Month): 2 (November)
|Contact details of provider:|| Postal: Bd.Expozitiei 1B, Bucuresti, Sector 1, Etaj 5, 012101|
Web page: http://www.rau.ro/
More information through EDIRC
When requesting a correction, please mention this item's handle: RePEc:rau:jisomg:v:2:y:2008:i:2:p:375-390. See general information about how to correct material in RePEc.
For technical questions regarding this item, or to correct its authors, title, abstract, bibliographic or download information, contact: (Alex Tabusca)
If references are entirely missing, you can add them using this form.