IDEAS home Printed from https://ideas.repec.org/
MyIDEAS: Login to save this article or follow this journal

Optimizing Large Combinational Networks For K-Lut Based Fpga Mapping

  • Ion I. BUCUR

    (University Politehnica of Bucharest)

  • Ioana FĂGĂRĂŞAN

    (University Politehnica of Bucharest)

  • Cornel POPESCU

    (University Politehnica of Bucharest)

  • George CULEA

    (University of Bacǎu, Faculty of Electrical Engineering)

  • Alexandru E. ŞUŞU

    (Swiss Federal Institute of Technology Lausanne)

Registered author(s):

    Optimizing by partitioning is a central problem in VLSI design automation, addressing circuit’s manufacturability. Circuit partitioning has multiple applications in VLSI design. One of the most common is that of dividing combinational circuits (usually large ones) that will not fit on a single package among a number of packages. Partitioning is of practical importance for k-LUT based FPGA circuit implementation. In this work is presented multilevel a multi-resource partitioning algorithm for partitioning large combinational circuits in order to efficiently use existing and commercially available FPGAs packages

    If you experience problems downloading a file, check if you have the proper application to view it first. In case of further problems read the IDEAS help page. Note that these files are not on the IDEAS site. Please be patient as the files may be large.

    File URL: http://www.rebe.rau.ro/RePEc/rau/jisomg/SU08/JISOM-SU08-A15.pdf
    Download Restriction: no

    Article provided by Romanian-American University in its journal Journal of Information Systems and Operation Management.

    Volume (Year): 2 (2008)
    Issue (Month): 1 (July)
    Pages: 154-165

    as
    in new window

    Handle: RePEc:rau:jisomg:v:2:y:2008:i:1:p:154-165
    Contact details of provider: Postal: Bd.Expozitiei 1B, Bucuresti, Sector 1, Etaj 5, 012101
    Phone: +4-0372-120.140
    Fax: +4-021-202.91.51
    Web page: http://www.rau.ro/
    Email:


    More information through EDIRC

    No references listed on IDEAS
    You can help add them by filling out this form.

    This item is not listed on Wikipedia, on a reading list or among the top items on IDEAS.

    When requesting a correction, please mention this item's handle: RePEc:rau:jisomg:v:2:y:2008:i:1:p:154-165. See general information about how to correct material in RePEc.

    For technical questions regarding this item, or to correct its authors, title, abstract, bibliographic or download information, contact: (Alex Tabusca)

    If you have authored this item and are not yet registered with RePEc, we encourage you to do it here. This allows to link your profile to this item. It also allows you to accept potential citations to this item that we are uncertain about.

    If references are entirely missing, you can add them using this form.

    If the full references list an item that is present in RePEc, but the system did not link to it, you can help with this form.

    If you know of missing items citing this one, you can help us creating those links by adding the relevant references in the same way as above, for each refering item. If you are a registered author of this item, you may also want to check the "citations" tab in your profile, as there may be some citations waiting for confirmation.

    Please note that corrections may take a couple of weeks to filter through the various RePEc services.

    This information is provided to you by IDEAS at the Research Division of the Federal Reserve Bank of St. Louis using RePEc data.