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Optimizing Large Combinational Networks For K-Lut Based Fpga Mapping


  • Ion I. BUCUR

    (University Politehnica of Bucharest)


    (University Politehnica of Bucharest)

  • Cornel POPESCU

    (University Politehnica of Bucharest)

  • George CULEA

    (University of Bacǎu, Faculty of Electrical Engineering)

  • Alexandru E. ŞUŞU

    (Swiss Federal Institute of Technology Lausanne)


Optimizing by partitioning is a central problem in VLSI design automation, addressing circuit’s manufacturability. Circuit partitioning has multiple applications in VLSI design. One of the most common is that of dividing combinational circuits (usually large ones) that will not fit on a single package among a number of packages. Partitioning is of practical importance for k-LUT based FPGA circuit implementation. In this work is presented multilevel a multi-resource partitioning algorithm for partitioning large combinational circuits in order to efficiently use existing and commercially available FPGAs packages

Suggested Citation

  • Ion I. BUCUR & Ioana FĂGĂRĂŞAN & Cornel POPESCU & George CULEA & Alexandru E. ŞUŞU, 2008. "Optimizing Large Combinational Networks For K-Lut Based Fpga Mapping," Journal of Information Systems & Operations Management, Romanian-American University, vol. 2(1), pages 154-165, July.
  • Handle: RePEc:rau:jisomg:v:2:y:2008:i:1:p:154-165

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    References listed on IDEAS

    1. Ion Lungu & Dana-Mihaela Petroşanu & Alexandru Pîrjan, 2011. "Solutions For Optimizing The Data Parallel Prefix Sum Algorithm Using The Compute Unified Device Architecture," Romanian Economic Business Review, Romanian-American University, vol. 5(2.1), pages 465-477, December.
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