Exploring hardware implementation feasibility of post-quantum cryptography in embedded systems: Evaluation of NIST-standardized ML-KEM, ML-DSA and SLH-DSA on ESP32-C6

The transition to post-quantum cryptography (PQC) raises practical concerns regarding the feasibility of standardized algorithms on resource-constrained embedded platforms. While National Institute of Standards and Technology (NIST)-selected PQC schemes are designed for broad applicability, their real-world performance on low-power microcontrollers remains insufficiently characterized. Using a configurable on-device evaluation framework, we assess the lattice-based key encapsulation mechanism (ML-KEM), lattice-based digital signature scheme (ML-DSA), and the hash-based digital signature scheme (SLH-DSA) implementations from the liboqs library across all NIST-standardized parameter sets and security levels. Our measurements focus on execution latency, key and signature material sizes, and dynamic memory behavior under realistic embedded constraints. Experimental results show that all evaluated ML-KEM, ML-DSA, and SLH-DSA parameter sets execute successfully on the ESP32-C6 without external memory support. ML-KEM exhibits stable and predictable memory usage across parameter sets, with execution time increasing proportionally with the security level. ML-DSA key generation and signing operations incur higher computational cost, while verification remains comparatively efficient. Evaluated SLH-DSA parameter sets demonstrate substantially higher execution latency, reflecting the inherent computational cost of hash-based signature schemes on embedded hardware. Overall, our results indicate that selected NIST PQC algorithms are deployable on modern embedded microcontrollers, provided that performance and latency trade-offs are carefully considered. The presented evaluation framework and empirical results provide practical guidance for the design of post-quantum secure embedded systems.