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A low power and low ripple CMOS high voltage generator for RFID transponder EEPROM

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  • Labonnah Farzana Rahman
  • Mohammad Marufuzzaman
  • Lubna Alam
  • Lariyah Mohd Sidek
  • Mamun Bin Ibne Reaz

Abstract

A high-voltage generator (HVG) is an essential part of a radio frequency identification electrically erasable programmable read-only memory (RFID–EEPROM). An HVG circuit is used to generate a regulated output voltage that is higher than the power supply voltage. However, the performance of the HVG is affected owing to the high-power dissipation, high-ripple voltage and low-pumping efficiency. Therefore, a regulator circuit consists of a voltage divider, comparator and a voltage reference, which are respectively required to reduce the ripple voltage, increase pumping efficiency and decrease the power dissipation of the HVG. Conversely, a clock driving circuit consists of the current-starved ring oscillator (CSRO), and the non- overlapping clock generator is required to drive the clock signals of the HVG circuit. In this study, the Mentor Graphics EldoSpice software package is used to design and simulate the HVG circuitry. The results showed that the designed CSRO dissipated only 4.9 μW at 10.2 MHz and that the phase noise was only -119.38 dBc/Hz at 1 MHz. Moreover, the proposed charge pump circuit was able to generate a maximum VPP of 13.53 V and it dissipated a power of only 31.01 μW for an input voltage VDD of 1.8 V. After integrating all the HVG modules, the results showed that the regulated HVG circuit was also able to generate a higher VPP of 14.59 V, while the total power dissipated was only 0.12 mW with a chip area of 0.044 mm2. Moreover, the HVG circuit produced a pumping efficiency of 90% and reduced the ripple voltage to

Suggested Citation

  • Labonnah Farzana Rahman & Mohammad Marufuzzaman & Lubna Alam & Lariyah Mohd Sidek & Mamun Bin Ibne Reaz, 2020. "A low power and low ripple CMOS high voltage generator for RFID transponder EEPROM," PLOS ONE, Public Library of Science, vol. 15(2), pages 1-14, February.
    • Handle: RePEc:plo:pone00:0225408
    DOI: 10.1371/journal.pone.0225408
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    1. Labonnah Farzana Rahman & Mamun Bin Ibne Reaz & Chia Chieu Yin & Mohammad Alauddin Mohammad Ali & Mohammad Marufuzzaman, 2014. "Design of High Speed and Low Offset Dynamic Latch Comparator in 0.18 µm CMOS Process," PLOS ONE, Public Library of Science, vol. 9(10), pages 1-12, October.
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