Design and Implementation of Efficient Multipliers using dual - Quality 4:2 Compressors

Reversible logic gates became very important and computing paradigm having its applications in low power CMOS technologies and Quantum computing we proposed reversible gates methodology also introduces for quantum cost reducing of circuit. Multiplier plays a vital role in many applications such as digital image processing, digital signal processing etc so it is important to design the multiplier with low power consumption and reduced delay. In order to reduce this factor we design the multiplier using four 4:2 compressor and these compressors has a switching mode and this is used to switch between the exact and approximate modes. In this paper, we introduce a novel architecture to perform high speed multiplication using ancient Vedic math techniques. A new high speed approach utilizing Dual quality 4:2 reverse compressor. The efficiencies of these compressors in a 16-bit multiplier are evaluated and by comparing their parameters with those of the state-of-the-art approximate multipliers. The results of comparison indicate, average lower delay and power consumption in the approximate mode. This paper is synthesized and simulated in XILINX software using verilog as hardware description language.