A High Performance of Low Power Primary Synchronization Signal Detection in LTE

This paper aims to maximize through put by minimizing power. One of the approaches to attain power reduction of MIMO OFDM system by optimizing FFT architecture which is addressed in this paper. Memory has crucial importance in MIMO OFDM transceivers which are costly due to their long delay and high power consumption. An important challenging task in LTE baseband receiver design is synchronization. Conventional algorithms are based on correlation methods that involve a large number of multiplications which leads to high receiver hardware complexity and power consumption. In this brief, a hardware-efficient synchronization algorithm for frame timing based clustering and a centrally symmetric synchronization signal, this offers low matched filter implementation complexity. This presents a new synchronization method for low power and low cost design. The approach of a 1-bit analog-to-digital converter (ADC) with down-sampling is compared with that of a 10-bit ADC without down-sampling under multi-path fading conditions defined in LTE standard for user equipment (UE) performance test. The algorithm reduces the complexity of the Primary synchronization signal for LTE. Structural realization and analysis pertaining to timing, power for high performance to detect PSS detection is derived.