IDEAS home Printed from https://ideas.repec.org/a/jbh/ijsrcs/v2y2017i2idhcseit1722216.html

Design of High-Speed Low Power Full Adder Using TFET

Author

Listed:
  • R. Gowtham Raj
  • V. Bakya Lakshmi

Abstract

A full adder circuit is considered as one of the fundamental building block for Digital Signal Processors (DSPs), Arithmetic and Logical Units (ALUs), Application Specific Integrated Circuits (ASICs) in VLSI design. So speed power and area are the three main design metrics for any VLSI circuits. The speed of the higher level design depends on the speed of full adder circuits. Thus realizing an efficient adder is required for better performance of an ALU and therefore the processor. A low power and high performance 1-bit full adder is proposed. In the existing system 8T NMOS full adder technique has been used. This NMOS full adder provides low speed and consumes more power. The major disadvantage is load capacitance effect. Compared to earlier designed NMOS full adder, the proposed TFET full adder shows a significant improvement in Power Delay Product (PDP), and speed. The simulation and power analysis are carried out using cadence virtuoso environment with 180 nm technology.

Suggested Citation

  • R. Gowtham Raj & V. Bakya Lakshmi, 2017. "Design of High-Speed Low Power Full Adder Using TFET," International Journal of Scientific Research in Computer Science, Engineering and Information Technology, International Journal of Scientific Research in Computer Science, Engineering and Information Technology, vol. 2(2), pages 681-685, April.
    • Handle: RePEc:jbh:ijsrcs:v2:y2017:i2:id:hcseit1722216
    Note: Article URL: https://ijsrcseit.com/CSEIT1722216
    as

    Download full text from publisher

    File URL: https://ijsrcseit.com/CSEIT1722216
    File Function: Article URL
    Download Restriction: no
    File URL: https://ijsrcseit.com/paper/CSEIT1722216.pdf
    File Function: Full text
    Download Restriction: no
    ---><---

    More about this item

    Keywords

    ;
    ;
    ;
    ;
    ;
    ;
    ;

    Statistics

    Access and download statistics

    Corrections

    All material on this site has been provided by the respective publishers and authors. You can help correct errors and omissions. When requesting a correction, please mention this item's handle: RePEc:jbh:ijsrcs:v2:y2017:i2:id:hcseit1722216. See general information about how to correct material in RePEc.

    If you have authored this item and are not yet registered with RePEc, we encourage you to do it here. This allows to link your profile to this item. It also allows you to accept potential citations to this item that we are uncertain about.

    We have no bibliographic references for this item. You can help adding them by using this form .

    If you know of missing items citing this one, you can help us creating those links by adding the relevant references in the same way as above, for each refering item. If you are a registered author of this item, you may also want to check the "citations" tab in your RePEc Author Service profile, as there may be some citations waiting for confirmation.

    For technical questions regarding this item, or to correct its authors, title, abstract, bibliographic or download information, contact: Pankaj Sharma (USA) (email available below). General contact details of provider: https://ijsrcseit.com/home .

    Please note that corrections may take a couple of weeks to filter through the various RePEc services.

    IDEAS is a RePEc service. RePEc uses bibliographic data supplied by the respective publishers.