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Design of 8T SRAM Cell Using Transmission Gates

Author

Listed:
  • Aditya Kulkarni
  • Lohan M
  • Sunitha S V
  • Shashank G Kubasad
  • Shriparna

Abstract

Around 70% of the power consumed and area occupied on a silicon die is due to SRAMs, which also take up about 70% of the total die space. This design provides a lower footprint, reduced latency, less expenditure of power, and increased data stability during read operations. System on Chips (SoCs) heavily relies on SRAMs, which usually take up about 70% of the total area of the die. This leaves room for potential expansion in the future. The usage of SRAMs has resulted in higher power demand, which can be addressed to the growth in the number of transistors and the associated leakage current that comes along with these transistors in smaller technologies.

Suggested Citation

  • Aditya Kulkarni & Lohan M & Sunitha S V & Shashank G Kubasad & Shriparna, 2025. "Design of 8T SRAM Cell Using Transmission Gates," International Journal of Scientific Research in Computer Science, Engineering and Information Technology, International Journal of Scientific Research in Computer Science, Engineering and Information Technology, vol. 11(2), pages 2314-2322, March.
    • Handle: RePEc:jbh:ijsrcs:v11:y2025:i2:id:1284
    DOI: 10.32628/CSEIT25112727
    Note: Article URL: https://ijsrcseit.com/home/article/view/CSEIT25112727
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