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Low Error Compensation Fixed width RPR Multiplier Design Using in Merging of Images

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  • N. Megala
  • N. Rajeswaran

Abstract

In area efficient low error compensation multiplier design is using fixed width RPR(Reduced Precision Redundancy). We propose a new method called fixed width RPR for DSP applications. This fixed width multiplier is placed in ANT architecture to meet high speed, low power consumption and area efficiency. The fixed RPR is designed with compensation circuit for minimizing the occurrence of error. The nxn bit is used as a input. The partial product term is used in RPR block for input correction vector and trivial input modification vector to worse the truncation errors. To achieve more precise error compensation. Variable correction value is used the truncation error can be compensation circuit is minimized. This circuit can be use in applications of image processing. By using this multiplier we merge the two images into compressed single image.

Suggested Citation

  • N. Megala & N. Rajeswaran, 2016. "Low Error Compensation Fixed width RPR Multiplier Design Using in Merging of Images," International Journal of Scientific Research in Science, Engineering and Technology, International Journal of Scientific Research in Science, Engineering and Technology, vol. 2(2), pages 261-264, December.
    • Handle: RePEc:ijs:ijsrse:v2:y2016:i2:id:hijsrset162241
    Note: Article URL: https://ijsrset.com/IJSRSET162241
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