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A Power-Efficient FPGA Test Pattern Composer

Author

Listed:
  • K. Pasipalana Rao
  • Ch. Hari Chandrika
  • G. Ramya Krishna
  • G. Anitha Iswarya

Abstract

The paper presents a novel approach to generating true random number sequences in Xilinx hardware using the random jitter of free-running oscillators. By employing programmable delay lines, the proposed method aims to reduce correlation between oscillator rings, enhancing randomness. Post- processing techniques such as Von-Neumann correction are applied to refine the generated sequences. Additionally, clock gating architecture is utilized to improve power efficiency by reducing switching activity. Notably, the design omits data and read/write lines in SRAM memory architecture due to LUT memory accessing not requiring write operations.

Suggested Citation

  • K. Pasipalana Rao & Ch. Hari Chandrika & G. Ramya Krishna & G. Anitha Iswarya, 2024. "A Power-Efficient FPGA Test Pattern Composer," International Journal of Scientific Research in Science, Engineering and Technology, Technoscience Academy, vol. 11(2), pages 333-341, April.
    • Handle: RePEc:ijs:ijsrse:v11:y2024:i2:id:58
    DOI: 10.32628/IJSRSET2411250
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