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Sensorless Dual TSEP ( V th , R dson ) Implementation for Junction Temperature Measurement in Parallelized SiC MOSFETs

Author

Listed:
  • Louis Alauzet

    (Icam School of Engineering, Toulouse Campus, 31300 Toulouse, France
    LAAS-CNRS, ESE, Université De Toulouse, 31031 Toulouse, France)

  • Patrick Tounsi

    (LAAS-CNRS, ESE, Université De Toulouse, 31031 Toulouse, France)

  • Jean-Pierre Fradin

    (Icam School of Engineering, Toulouse Campus, 31300 Toulouse, France)

Abstract

This article presents a method for detecting the temperature distribution of two parallelized Silicon Carbide (SiC) MOSFETs. Two thermally sensitive electrical parameters (TSEPs), namely the on-state resistance ( R d s o n ) and the threshold voltage ( V t h ), are introduced. A comparison of the temperatures interpolated by V t h and R d s o n shows disparity, enabling the detection of individual junction temperatures. V t h instability and its measurement are discussed for SiC devices. Experimental results show that, depending on the instability of the V t h and the sensitivity of the two TSEPs at certain temperatures, a combination of different TSEPs could be a solution for extracting the maximum junction temperature of parallelized devices.

Suggested Citation

  • Louis Alauzet & Patrick Tounsi & Jean-Pierre Fradin, 2025. "Sensorless Dual TSEP ( V th , R dson ) Implementation for Junction Temperature Measurement in Parallelized SiC MOSFETs," Energies, MDPI, vol. 18(13), pages 1-15, July.
  • Handle: RePEc:gam:jeners:v:18:y:2025:i:13:p:3470-:d:1692457
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