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Field Plate Integration for Mitigating Partial Discharge Activity in PCB-Embedded Power Electronic Modules

Author

Listed:
  • Paul Bruyere

    (Université Grenoble Alpes, CNRS, Grenoble INP, G2Elab, 38000 Grenoble, France
    Universite Claude Bernard Lyon 1, INSA Lyon, CNRS, Ecole Centrale de Lyon, Ampère, UMR5005, 69130 Ecully, France)

  • Eric Vagnon

    (Universite Claude Bernard Lyon 1, INSA Lyon, CNRS, Ecole Centrale de Lyon, Ampère, UMR5005, 69130 Ecully, France)

  • Yvan Avenas

    (Université Grenoble Alpes, CNRS, Grenoble INP, G2Elab, 38000 Grenoble, France)

Abstract

This paper proposes a concept based on field plate (FP) integration inside printed circuit board (PCB)-embedded power modules. The goal is to reduce the electric field at their surface and thus increase the partial discharge inception voltage (PDIV). Electrostatic simulations are first carried out to analyze the electric field reduction induced by the use of FPs. Then, dedicated experiments are proposed to demonstrate that the actual PDIV increases in AC sinus 50 Hz when FPs are implemented. More specifically, it is observed that an optimal FP length exists. Several analyses based on simulations and experiments are thus proposed to explain this phenomenon. Finally, an assessment of PD activity and PD location is presented to support the analysis. AC sinus 50 Hz characterizations indicate that PDIV can be increased by 178% compared to PCBs without FPs with a proper definition of equipotential prolongation and PCB length.

Suggested Citation

  • Paul Bruyere & Eric Vagnon & Yvan Avenas, 2024. "Field Plate Integration for Mitigating Partial Discharge Activity in PCB-Embedded Power Electronic Modules," Energies, MDPI, vol. 17(9), pages 1-20, April.
    • Handle: RePEc:gam:jeners:v:17:y:2024:i:9:p:2035-:d:1382957
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