An Event-Driven Self-Clocked Digital Low-Dropout Regulator with Adaptive Frequency Control

Digital low-dropout (DLDO) is widely used for power management in the system-on-chip (SoC) because of its low-voltage operation and process scalability. However, conventional DLDOs suffer from the trade-off between transient response and power consumption of the DLDO and the clock generator. This paper proposes an event-driven self-clocked DLDO regulator. The proposed low quiescent current (I Q ) event-driven adaptive frequency clock generator (EACG) adapts its frequency in different load conditions without a current sensor or complex compensation circuit for stable operation in the entire load range. The proposed DLDO does not need any external clocking signal and can maintain low output ripple and low power consumption in the steady-state. The clock-less transient detector (CLTD), consisting of two clock-independent transient detection paths, uses power more efficiently and improves the transient response significantly without sacrificing the power consumption. This work was fabricated in a 40 nm CMOS process with an 0.3 nF on-chip capacitor. The measurement results show that with the step load current between 1 mA and 60 mA, the proposed DLDO achieves a transient recovery time of 220 ns. The total I Q of the proposed DLDO is only 26 μA in steady-state, and it achieves stable operation in the entire load range.