Performance of Parallel Connected SiC MOSFETs under Short Circuits Conditions

This paper investigates the impact of parameter variation between parallel connected SiC MOSFETs on short circuit (SC) performance. SC tests are performed on parallel connected devices with different switching rates, junction temperatures and threshold voltages ( V TH ). The results show that V TH variation is the most critical factor affecting reduced robustness of parallel devices under SC. The SC current conducted per device is shown to increase under parallel connection compared to single device measurements. V TH shift from bias–temperature–instability (BTI) is known to occur in SiC MOSFETs, hence this paper combines BTI and SC tests. The results show that a positive V GS stress on the gate before the SC measurement reduces the peak SC current by a magnitude that is proportional to V GS stress time. Repeating the measurements at elevated temperatures reduces the time dependency of the V TH shift, thereby indicating thermal acceleration of negative charge trapping. V TH recovery is also observed using SC measurements. Similar measurements are performed on Si IGBTs with no observable impact of V GS stress on SC measurements. In conclusion, a test methodology for investigating the impact of BTI on SC characteristics is presented along with key results showing the electrothermal dynamics of parallel devices under SC conditions.