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Efficient FPSoC Prototyping of FCS-MPC for Three-Phase Voltage Source Inverters

Author

Listed:
  • Eduardo Zafra

    (Departamento de Ingeniería Electrónica, Escuela Técnica Superior de Ingeniería, Universidad de Sevilla, Camino de los Descubrimientos s/n, 41092 Seville, Spain)

  • Sergio Vazquez

    (Departamento de Ingeniería Electrónica, Escuela Técnica Superior de Ingeniería, Universidad de Sevilla, Camino de los Descubrimientos s/n, 41092 Seville, Spain)

  • Hipolito Guzman Miranda

    (Departamento de Ingeniería Electrónica, Escuela Técnica Superior de Ingeniería, Universidad de Sevilla, Camino de los Descubrimientos s/n, 41092 Seville, Spain)

  • Juan A. Sanchez

    (Departamento de Ingeniería Electrónica, Escuela Técnica Superior de Ingeniería, Universidad de Sevilla, Camino de los Descubrimientos s/n, 41092 Seville, Spain)

  • Abraham Marquez

    (Departamento de Ingeniería Electrónica, Escuela Técnica Superior de Ingeniería, Universidad de Sevilla, Camino de los Descubrimientos s/n, 41092 Seville, Spain)

  • Jose I. Leon

    (Departamento de Ingeniería Electrónica, Escuela Técnica Superior de Ingeniería, Universidad de Sevilla, Camino de los Descubrimientos s/n, 41092 Seville, Spain
    Department of Control Science and Engineering, Harbin Institute of Technology, Harbin 15001, China)

  • Leopoldo G. Franquelo

    (Departamento de Ingeniería Electrónica, Escuela Técnica Superior de Ingeniería, Universidad de Sevilla, Camino de los Descubrimientos s/n, 41092 Seville, Spain
    Department of Control Science and Engineering, Harbin Institute of Technology, Harbin 15001, China)

Abstract

This work describes an efficient implementation in terms of computation time and resource usage in a Field-Programmable System-On-Chip (FPSoC) of a Finite Control Set Model Predictive Control (FCS-MPC) algorithm. As an example, the FCS-MPC implementation is used for the current reference tracking of a two-level three-phase power converter. The proposed solution is an enabler for using both complex control algorithms and digital controllers for high switching frequency semiconductor technologies. An original HW/SW (hardware and software) system architecture for an FPSoC is designed to take advantage of a modern operating system, while removing time uncertainty in real-time software tasks, and exploiting dedicated FPGA fabric for the most complex computations. In addition, two different architectures for the FPGA-implemented functionality are proposed and compared in order to study the area-speed trade-off. Experimental results show the feasibility of the proposed implementation, which achieves a speed hundreds of times faster than the conventional Digital Signal Processor (DSP)-based control platform.

Suggested Citation

  • Eduardo Zafra & Sergio Vazquez & Hipolito Guzman Miranda & Juan A. Sanchez & Abraham Marquez & Jose I. Leon & Leopoldo G. Franquelo, 2020. "Efficient FPSoC Prototyping of FCS-MPC for Three-Phase Voltage Source Inverters," Energies, MDPI, vol. 13(5), pages 1-16, March.
    • Handle: RePEc:gam:jeners:v:13:y:2020:i:5:p:1074-:d:326749
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    Citations

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    Cited by:

    1. Patryk Chaber & Andrzej Wojtulewicz, 2022. "Flexible Matrix of Controllers for Real Time Parallel Control," Energies, MDPI, vol. 15(5), pages 1-23, March.
    2. Deepa Sankar & Lakshmi Syamala & Babu Chembathu Ayyappan & Mathew Kallarackal, 2021. "FPGA-Based Cost-Effective and Resource Optimized Solution of Predictive Direct Current Control for Power Converters," Energies, MDPI, vol. 14(22), pages 1-26, November.
    3. Roberto O. Ramírez & Carlos R. Baier & Felipe Villarroel & Eduardo Espinosa & Mauricio Arevalo & Jose R. Espinoza, 2023. "Reduction of DC Capacitor Size in Three-Phase Input/Single-Phase Output Power Cells of Multi-Cell Converters through Resonant and Predictive Control: A Characterization of Its Impact on the Operating ," Mathematics, MDPI, vol. 11(14), pages 1-19, July.
    4. David Sotelo & Antonio Favela-Contreras & Alfonso Avila & Arturo Pinto & Francisco Beltran-Carbajal & Carlos Sotelo, 2022. "A New Software-Based Optimization Technique for Embedded Latency Improvement of a Constrained MIMO MPC," Mathematics, MDPI, vol. 10(15), pages 1-19, July.

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