Security Enhancement in Digital Circuits Using Probabilistic Delay Insertion and Timing Obfuscation

This paper presents a probabilistic delay insertion–based approach for timing obfuscation in digital circuit design using DSCH and MICROWIND tools. The proposed architecture integrates probabilistic multiplexer logic, key-controlled selection, delay elements, and feedback stabilization to introduce controlled randomness in signal propagation while preserving functional correctness. The effectiveness of the approach is evaluated through analog simulations, focusing on power and timing behavior. Simulation results show that basic probabilistic logic exhibits low power consumption of 1.34 µW, while key-controlled probabilistic selection increases power to 2.32 µW due to enhanced switching activity. The integration of probabilistic delay elements reduces average power to 1.41 µW by spreading signal transitions over time, achieving efficient timing obfuscation. The feedback-stabilized configuration provides maximum security with a measured power of 2.92 µW, reflecting the trade-off between robustness and power overhead. Overall, the results demonstrate that probabilistic delay insertion enables effective timing obfuscation with acceptable power consumption, making the proposed method suitable for secure and low-power digital circuit applications.